An Adaptive Body-Biased Low-Leakage SRAM Cache

In this project, we present an adaptive body biasing scheme for standby leakage reduction in the cache memories. During standby, the memory cells are in reverse body bias mode while during active mode a selected portion of the memory cells are driven to zero body bias. The main advantage of this scheme is zero delay penalty when compared to conventional design because of the fact that the cells are at zero body bias when accessed. The transition latency i.e. the delay to wake up the selected memory from reverse body bias to the zero body bias, is minimized using pipeline for the address decoder and the data path. We also present a technique for driver down-sizing when we have room to increase the memory wake up time without increasing the overhead on the pipeline. Experimental result indicates on an average a reduction of 28% of leakage power as compared to the conventional cache.